Course Details

VPI-PLI With Verilog (VPLI) is a course designed to introduce you to one of the most popular foreign language interface to Verilog i.e. the Verilog Procedural Interface (VPI) or Programming Language Interface (PLI) version 2.0. Most of the verification environment in companies today is built around C++ and SystemVerilog together interacting with Verilog RTL. However, these environments are built in such a way that a large number of users never get to know the guts of how this whole environment operates. An understanding of what happens behind the scenes in such a verification environment is essential knowledge if one wishes to move up the value chain.

This is not an advanced course on VPI and it does not cover SystemVerilog’s Direct Programming Interface (DPI). The course introduces essential topics on VPI through small examples so that a student is able to understand what is really happening. Toward the end two complete examples are taken: One is a C++ based Verification environment and the other is a X-injector. We will make use of public domain Icarus Verilog simulator and GTKWave waveform viewer for the various exercises. This course can be completed in less than a week’s time.

Highlights

1. Strong focus on hands-on programming experience
2. Gain insight into how a typical chip verification environment works
3. Develop familiarity with most of the common VPI routines
4. Discuss with the instructors on the forums as much as you want

Instructors and Forum Moderators

This course is taught by Anup Gangwar. He will also be moderating the course forums.

Pre-requisites

This course assumes a sufficient background with Verilog, the 'C++' programming language, and good familiarity with programming on GNU/Linux. If you have experience in working with any other UNIX system, then it is fine too. In case you do not have the required background, we recommend that you take up the courses User Level Linux and Programming With C++ to gain sufficient background before taking up this course. At this point of time we do not have any offering for Verilog and that skill you must pick up elsewhere.

Who should take the course

• Students who wish to join semiconductor/EDA companies
• Professionals who wish to gain more insight into how a typical chip verification environment operates

Depth

This course is at an intermediate level. Most of the topics are treated at a reasonable depth. Goal is to expose you to the various pieces of VPI so that you are able to gather more information on your own as needed.

Detailed Description

1. Introduction
   • Typical simulation setup for verification
   • HDL simulation overview
   • Event driven simulation
   • Foreign language interface
   • Verification environments comparison
2. Verilog procedural interface
   • How design is represented internally
   • Walks on a tree
   • Depth-first walk
   • Breadth-first walk
   • What is VPI
3. Common VPI routines
   • Basic VPI application
   • Getting simulation time
   • Getting properties
   • Iterating over elements
   • Getting values
   • Setting values
   • Terminating simulation
   • Avoiding memory leaks
4. Exporting C functions to Verilog
   • Exporting as a task
   • Exporting as a function
   • Moving data between Verilog and C
5. Attaching to simulator transparently from C
   • Concept of callbacks
   • Calling at simulation start and simulation end
   • Calling at simulation boundaries
6. Verilog and C++ based verification environment
   • Class hierarchy
   • Interface for simulation callbacks
   • Accessing and modifying RTL values
7. X-injector using VPI
   • Walking over the RTL hierarchy
   • Limitations and pitfalls of this design
8. Wrapping up the module
   • Relevant links
   • Good books on VPI

The objective of this course as outlined above is to help you gain more insight into VPI. After finishing this course, you will be able to gain invaluable insight into the guts of most of the verification environments.